1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to the manufacture of metallization layers including conductive materials, such as copper, embedded into a dielectric material.
2. Description of the Related Art
In an integrated circuit, a very large number of circuit elements, such as transistors, capacitors, resistors and the like, are formed in or on an appropriate substrate, usually in a substantially planar configuration. Due to the large number of circuit elements and the required complex layout of advanced integrated circuits, the electrical connections of individual circuit elements are generally not established within the same level on which the circuit elements are manufactured. Typically, such electrical connections are formed in one or more additional “wiring” layers, also referred to as metallization layers. These metallization layers generally include metal-containing lines, providing the inner-level electrical connection, and also include a plurality of inter-level connections, also referred to as vias, that are filled with an appropriate metal. Thus, the vias provide the electrical connection between two neighboring stacked metallization layers.
Due to the continuous reduction of feature sizes of circuit elements in modern integrated circuits, the number of circuit elements for a given chip area, that is, the packing density, also increases, thereby requiring an even larger increase in the number of electrical interconnections to provide the desired circuit functionality. Therefore, the number of stacked metallization layers may increase and the dimensions of the individual lines and vias may be reduced as the number of circuit elements per chip area becomes larger. The vias may typically be formed by etching an opening into a respective interlayer dielectric material, which in sophisticated applications may be a low-k material or an ultra-low-k (ULK) material having a dielectric constant of 2.7 and less. In combination with these highly sensitive dielectric materials, a highly conductive metal, such as copper or copper alloys, is used that is subsequently filled into the opening, typically together with an appropriate conductive barrier material. Due to the reduced dimensions of the vias, sophisticated anisotropic etch techniques are usually necessary for forming the high aspect ratio openings.
For example, in sophisticated semiconductor devices, the vias or trenches in lower-lying metallization layers have to comply with the high packing density that is realized in the device level, i.e., in and above the semiconductor material in which transistors, capacitors, resistors and the like are formed on the basis of a semiconductor material. Consequently, the vias and trenches to be formed in the dielectric material may have a dimension in at least one lateral dimension that is 100 nm and less, while a thickness of the interlayer dielectric material may be several hundred nanometers, thereby yielding an aspect ratio, i.e., a ratio of depth to width, of any such openings of 5 and significantly higher. Hence, sophisticated plasma assisted anisotropic etch recipes have to be applied in combination with complex patterning strategies, i.e., sophisticated lithography processes and hard mask regimes, since typically a resist material cannot be provided with sufficient thickness so as to act as an etch mask for etching through the entire interlayer dielectric material. It has been observed that the patterning of the interlayer dielectric material may result in significant particle contamination and thus yield loss, which is, to a large extent, due to plasma-induced damage that occurs during the etch process. Basically, during plasma etching, reactive ions are created and are accelerated towards the surface to be treated in order to obtain a high directionality for providing a moderately high physical removal component of the incoming ions so that a substantially perpendicularly oriented removal component in combination with the chemical interaction of the reactive ions is achieved.
Moreover, as discussed above, high aspect ratio openings are typically to be formed, thereby requiring additional measures for controlling the lateral etch rate within the high aspect ratios. To this end, appropriate precursor materials may be added to the etch atmosphere in order to form polymer compounds that significantly reduce a lateral etching rate, while substantially not affecting the vertical progress of the corresponding etch front. Due to the very complex conditions within the plasma etch atmosphere, increasingly, positive ions accumulate in a lower portion of the etched openings, while negative charge accumulates in an upper portion thereof, thereby increasingly building up a vertical potential difference. Consequently, due to the highly local separation of positive and negative charges a localized potential difference is created in the vicinity of corresponding openings, wherein the potential difference, thus, may significantly depend on the aspect ratio, the local neighborhood, i.e. pattern density, and the like. In particular, the effect of a significant potential difference is particularly pronounced in situations in which dielectric material is increasingly removed from above a conductive area, such as a metal region of a lower-lying metallization layer. Consequently, upon reaching a certain critical thickness of the dielectric material, the potential difference may result in a dielectric breakdown of the remaining dielectric material, i.e., a non-controlled discharge occurs, which is also referred to as an arcing event. In this case, a significant amount of particles may be generated, for instance in the form of “burned” dielectric material, metal material and the like, wherein these particles are typically distributed over a wide area of the semiconductor substrate, thereby significantly increasing the overall contamination, which in turn may result in significant yield losses, or may at least cause a deterioration of reliability of the resulting semiconductor devices. Thus, the frequency of the occurrence of arcing events may significantly affect the yield per substrate, wherein, however, the occurrence of these events is difficult to predict since a plurality of factors may play an important role, such as plasma instabilities, the overall surface structure conditions, such as pattern density, the presence of lower-lying metal regions and their size and the like. For instance, the frequency of arcing events during dielectric etch processes may be extremely low in the absence of any lower-lying metal regions, wherein a significant increase of the frequency of these events is observed during the formation of metallization structures of sophisticated semiconductor devices.
As discussed above, in particular the process of forming vias may result in significant plasma-induced damage, since here the vertical potential difference may result in an increasing voltage across the very thin dielectric material upon finally clearing the bottom surface of the openings. That is, typically, a main etch process is performed so as to etch through the interlayer dielectric material, which in sophisticated applications is provided in the form of a low-k dielectric material or a ULK material, as discussed above, while, in a final phase of the etch sequence, the etch conditions are typically changed upon exposing an etch stop material and etching through this material, thereby also requiring a certain length of an over-etch time in order to reliably remove the material in any of the openings, since the etch rate may also significantly depend on the local conditions across the substrate. In this case, faster etching circuit features may encounter a thinned dielectric material on the basis of the same global plasma conditions, which may thus result in a high probability of creating a dielectric breakdown of the resulting thin dielectric material immediately prior to completely clearing the corresponding interface formed with the lower-lying metal region.
Observations indicate that the occurrence of arcing events is highly correlated with certain areas in the substrate, wherein, in particular, the wafer edge has been identified as a source of frequent arcing events. Consequently a plurality of “geometric” remedies for the occurrence of wafer edge related etch damage has been proposed, such as a change of the etch die exposure, in which non-yielding semiconductor die are substantially excluded from being exposed during the lithography process, thereby, however, contributing to a significantly reduced throughput caused by the reduced lithography capacity. In other cases, the resist material at the wafer edge may be applied in a more restricted manner, thereby, however, contributing to alignment problems. Also, the metal layers, such as copper layers, may be provided with increased exclusion zones, which, however, may result in increased material delamination at the wafer bevel, which in turn also significantly contributes to particle generation and thus yield losses.
In other approaches for reducing plasma-induced damage, generally the plasma conditions may be modified, for instance, by generally reducing the plasma power and increasing the process pressure of the plasma atmosphere during the etch process, which, however, may also reduce throughput and also contradicts other constraints of the plasma etch process, in which higher plasma density and high pressure is favored so as to obtain superior etch profiles and the like.
Typically, a plurality of plasma etch regimes are used in the field of semiconductor fabrication, wherein, however, in sophisticated plasma etch processes, often a so-called dual frequency regime may be applied in which electromagnetic power is supplied to the etch atmosphere on the basis of two different radio frequencies (RF). For example, a high frequency component having a frequency of several MHz to some GHz may be applied so as to substantially provide a plasma from a given carrier gas, i.e., ions and separated electrons, while a lower frequency of several hundred kHz to several MHz may be used to establish a desired bias voltage between the actual plasma and the substrate. In combination with appropriately selected reactive species and by adjusting the overall pressure in the etch atmosphere, the desired anisotropic etch behavior is obtained, wherein it should be appreciated that the configuration of a corresponding plasma reactor may also have a significant influence. On the other hand, irrespective of the geometric configuration of the plasma reactor, in particular, the electromagnetic power supplied with different radio frequencies represents a promising control mechanism for adjusting the overall plasma conditions and thus etch results, wherein any such control mechanisms may readily be applied to any given reactor configuration.
In view of the situation described above with reference to plasma etch conditions for patterning sophisticated metallization systems of semiconductor devices, the present disclosure relates to techniques for efficiently controlling sophisticated plasma etch processes, while avoiding or at least reducing one or more of the effects identified above.